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This page contains information about the Cadence design tools (Custom IC) used extensively in our analog and digital integrated circuit engineering classes. The Integrated Circuit Engineering (ECE345) class runs in the Spring Semester of the academic year. Each pair of students usually submits one or more circuits to a foundry for fabrication under the auspices of the MOSIS organization.

With funding from the Keck Foundation, an Integrated Circuit Engineering laboratory was established in 1994 with state-of-the-art computer-aided design (CAD) tools, computer platforms and their peripherals for the design of VLSI (Very Large Scale Integration) circuits. Integrated circuits, comprising from 20 to 20,000 transistors are designed from the bottom up using industry standard layout and simulation tools from Cadence Design Systems – made available at a massive discount through their educational program. The hardware has been upgraded many times these past twenty years – the speed of the network going from 10 Mbits/sec to 1 Gbit/sec with twelve Dell Vostro 220 computers purchased in 2009 to replacing aging self-assembled workstations. These ongoing changes have considerably reduced the design time.

The Integrated Circuit Design Experience

Students, working in pairs to comply with MOSIS funding regulations, undertake four design exercises using MOS transistors. The final circuits are sometimes fabricated through the MOSIS service. The first design exercise, DE1, moves the student, from transistors with fixed size to a design process in which the aspect ratio is an integral part of the design process. DE2 takes the student from circuits in schematic form, to the transistor as a planar device with a specific geometric pattern. The exercise comprises three circuits with increasing complexity. A simple inverting amplifier, with a diode connected transistor as the load, is followed by an inverting amplifier with an active current source as the load. Specifications are limited to gain, slew rate, supply voltage and fabrication technology. Students use supplied small signal models to set the sizes of the transistors. After layout, the circuit is extracted and re-simulated with attention paid to frequency response and the influence of parasitic capacitance. The amplifier with an active current source load presents more of a challenge because the design of the biasing circuit is very much in the hands of the student. The principal outcomes of this assignment are familiarity with the layout and simulation software, and an appreciation that the software is merely a tool used by the circuit designer.

The final part of DE2 is a simple operational transconductance amplifier. The circuit is supplied with specifications still limited to overall gain and slew rate, with guidelines for quiescent current and goals for the CMRR, PSRR and frequency response. This exercise rapidly introduces the student to the concept and reality of compromise in integrated circuit engineering. The open-ended nature of the exercise usually presents a significant challenge to most students. During its execution, they gain confidence in design and start to learn the art of compromise.

DE3 is presented as a set of specifications for a complete operational amplifier with internal frequency compensation. Values for the open loop gain, unity gain frequency and phase margin must be met by the circuit; other parameters such as the CMRR, output voltage swing and common mode input range must satisfy minimum requirements but improvements are strongly encouraged. This exercise introduces a variety of scenarios into the design experience. Students start to appreciate that numerical simulation packages such as Spectre often require intelligent intervention to achieve satisfactory convergence. The need to meet specifications, which often appear to be mutually exclusive, encourages the student to adopt a methodical approach to design. Within this exercise, there is a great deal is of latitude in the design process. The architecture of the amplifier is decided by the student as is the attention paid to layout. It is emphasized that the greater the effort expended in this assignment, the easier the final project will be. The outcome of DE3 is a thorough grounding in the principles of integrated circuit engineering. The reward of a working amplifier, complete with layout, provides compensation for a tough exercise.

Design Exercise 4 is a MAD (mixed analog and digital) circuit. Currently, this is a phase locked loop with a center frequency of 1GHz and a locking frequency range of 950MHz to 1.05GHz. The overall goal remaining is to design a PLL that responds rapidly to frequency jumps of 100MHz, achieves frequency and phase lock with minimum settling time and has a very stable output frequency. The first task of each group is to design a phase to frequency detector with a minimum deadband – a demanding digital design exercise. This is followed by slightly less formidable challenges for the charge pump and voltage controlled oscillator. The PLL is a considerable project for junior EE students and the accomplishment of phase and frequency lock in layout is usually accompanied by a shriek of eureka!

Previous circuits have included a four-bit flash ADC, implemented with between 400 and 500 MOS transistors and a three-bit ADC with an on board bandgap voltage reference. The ADC specifications include the input voltage range, sensitivity and the operating conditions. The overall goal remaining is to design the device to operate as fast as possible at 100°C. The first task of each group was the design of a comparator within which positive feedback is used to achieve the highest gain with minimum propagation delay. Since this is to be used as a standard cell, great attention is paid to layout both from the perspective of interconnection and isolation of analog and digital signals. The final part of the design was a thermometer decoder for the output of the comparator stack.

Integrated Circuit Engineering (ECE345)

Students entering this class are equipped with an understanding of the fundamental building blocks of analog integrated circuits and a thorough comprehension of frequency response and feedback. Focussing on analog design, the assignments for this class comprise a series of design exercises in which circuits are designed and laid out from the transistor level up. The first major circuit is an operational amplifier, chosen to bring together feedback, frequency response and blocks of transistors as circuit components. The other major exercise is a self-contained, a phase-locked loop.

Integrated circuit fabrication and technology. Device modeling, thermal effects. VLSI CAD design tools. Circuit layout, extraction and simulation. Design and analysis of multistage MOS operational amplifiers, OTA architectures. Nonlinear circuits, comparators. Analog switches. Sample and hold circuits. Bandgap reference circuits. MOS digital circuit design and layout, hierarchical approaches. Final design project is a mixed analog/digital circuit, e.g. a phase-locked loop.

Digital Integrated Circuit Engineering (ECE441)

Design of CMOS combinational logic gates, layout and simulation. Standard cell construction. State machines. Complex gate design. Sequential logic systems, clocks. Design of arithmetic building blocks, multipliers, memory, FPGAs. System design and HDLs. Floor-planning. System architecture. Term project to design and fabricate of an ASIC using a variety of VLSI CAD tools.

MOSIS Fabrication Processes

Past designs were fabricated using the ON C5 process with the NCSU Design Kit; in 2012 we moved to the IBM 7RF process using the commercially available design kit, in 2016 we fabricated two 1GHz PLL designs using the Global Foundries 7HV process. This year (2018) we move to the TSMC 180µm process.

Analog Design Examples

3 Bit Flash ADC (1.5µm)

4 Bit Flash ADC (0.5µm)

Phase Locked Loop (0.18µm)

















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